Description: 使用Verilog语言实现的RISC精简指令集CPU IP核,该CPU具有32位数据宽度,5级流水线结构和指令预判和中断处理功能,适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction pre-judgment and interrupt handling functions for Verilog language learners in depth reference. Platform: |
Size: 33792 |
Author:张秋光 |
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Description: 用verilog实现的一个基于流水线结构的正余弦信号发生器,六级流水线-Verilog realize a pipeline structure of the sine and cosine signal generator , six pipeline Platform: |
Size: 1024 |
Author:郭良谦 |
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Description: MIPS pipeline datapath Figure 6.30 in Paterson and Hennessy s textbook [4]. The model will be ... Listing 1.1: Verilog code for the multiplexer. A00000AA Platform: |
Size: 351232 |
Author:he |
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Description: 用verilog实现一个基于流水线结构的正、余弦信号发生器-Based on Pipeline Structure verilog to achieve a sine and cosine signal generator Platform: |
Size: 1024 |
Author:张山 |
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Description: 这是我们设计的一个MIPS流水线CPU,基于Verilog HDL语言实现。它与传统的MIPS流水线CPU不同点在于,5个流水段各自维护一个变量(SelType)表明当前正在执行的指令类型,这样处理数据冒险、loaduse冒险或者跳转冒险时候每个段都能知道其他段正在处理的语句,从而方便我们的处理。-This is a MIPS pipelined CPU based on Verilog HDL language to achieve. It the the MIPS pipelined CPU differences that each of the five pipeline stages maintenance a variable (SelType) indicates that the currently executing instruction types, this treatment data Adventure loaduse adventure or jump adventure when each segment can know The statement is being processed, in order to facilitate our processing. Platform: |
Size: 11357184 |
Author:武翔宇 |
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Description: verilog浮点乘发器,特定数据结构,指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline Platform: |
Size: 4096 |
Author:GTONJu |
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Description: verilog浮点乘发器,特定数据结构,指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline Platform: |
Size: 6144 |
Author:theCPI |
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Description: The logic design of an efficient and fast round robin arbiter in Verilog or any other HDL language relies on the capability to find the next requestor to grant without losing cycles and with minimal logical stages. Using the fastest logic constructs like Parallel Prefix Computation (PPC) and the most suitable architecture will result in a fast and efficient arbiter suitable for pipeline integration of a multiple queue structure Platform: |
Size: 1024 |
Author:thanh |
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Description: 流水线结构是在逻辑很复杂的情况下使用,通过分栈,把一个复杂的逻辑分成若干个比较简单的块实现,减少信号的逻辑级,提高频率。最形象的实例就是位宽较大的加法器。此程序就是verilog的实现
-In the pipeline structure is complex logic case, through the sub-stack, the complex logic into a plurality of blocks of a relatively simple implementation, the logic level signal decrease, increase frequency. The most vivid example is the bit width larger adder. This program is the realization of verilog Platform: |
Size: 229376 |
Author:jodyql |
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